
      device zxspectrum48

BEGIN:

      org 0x0000
      di
      jr  start

      org 0x0008

      org 0x0010
      out (0xff),a
      ret

      org 0x0018
      ret

      org 0x0020
      reti

      org 0x0028
      retn

      org 0x0030

      org 0x0038
      reti


start:
      ld    hl, STACK
      ld    sp, hl

      nop
      nop
      
      ld    hl,0
      ld    de,0
      ld    bc,0
      push  bc
      pop   af
      ld    ix, 0
      ld    iy, 0
      
      push  hl
      push  de
      push  bc
      exx
      pop   bc
      pop   de
      pop   hl
      exx
      
      ei

      call  test_01
      call  test_02
      call  test_03
      call  test_04
      call  test_05
      call  test_06
      call  test_07
      call  test_08
      call  test_09
      call  test_10
      call  test_11
      call  test_12
      call  test_13
      call  test_14
      call  test_15
      call  test_16
      call  test_17


stop:       
      halt
      jr  stop

tst_b:
      db 0
tst_b1:
      db 0
tst_b2:
      db 0
tst_b3:
      db 0

tst_w:
      dw 0

buf_b:
      ds 16
      
buf_e equ buf_b + 15
      
      
test_01:
      ld    a, 0x01
      out   (0x01),a

      ld    a, 0x07
      ld    (hl), a

      ld    bc, 0x0102
      ld    de, 0x0304
      ld    hl, 0x0506
      
      // ld a,r
      
      ld    a, b
      ld    a, c
      ld    a, d
      ld    a, e
      ld    a, h
      ld    a, l
      
      ld    hl, tst_b
      ld    a, (hl)
      ld    a, a
      
      
      // ld b, r
      ld    a, 0x07
      
      ld    b, b
      ld    b, c
      ld    b, d
      ld    b, e
      ld    b, h
      ld    b, l
      
      ld    hl, tst_b
      ld    b, (hl)
      ld    b, a

      // ld c,r
      ld    b, 0x01
      
      ld    c, b
      ld    c, c
      ld    c, d
      ld    c, e
      ld    c, h
      ld    c, l
      
      ld    hl, tst_b
      ld    c, (hl)
      ld    c, a
      
      // ld d,r
      ld    c, 0x02
      
      ld    d, b
      ld    d, c
      ld    d, d
      ld    d, e
      ld    d, h
      ld    d, l
      
      ld    hl, tst_b
      ld    d, (hl)
      ld    d, a
      
      // ld e, r
      ld    d, 0x03
      
      ld    e, b
      ld    e, c
      ld    e, d
      ld    e, e
      ld    e, h
      ld    e, l
      
      ld    hl, tst_b
      ld    e, (hl)
      ld    e, a
      
      // ld h, r
      ld    e, 0x04
      
      ld    h, b
      ld    h, c
      ld    h, d
      ld    h, e
      ld    h, h
      ld    h, l
      
      ld    hl, tst_b
      ld    h, (hl)
      ld    h, a
      
      // ld l, r
      ld    h, 0x05
      
      ld    l, b
      ld    l, c
      ld    l, d
      ld    l, e
      ld    l, h
      ld    l, l
      
      ld    hl, tst_b
      ld    l, (hl)
      ld    l, a
      
      // ld (hl), r
      ld    hl, tst_b
      
      ld    (hl), b
      ld    (hl), c
      ld    (hl), d
      ld    (hl), e
      ld    (hl), h
      ld    (hl), l     
      ld    (hl), a

      ld    ix, tst_b
      
      ld    (ix+0), b
      ld    (ix+1), c
      ld    (ix+2), d
      ld    (ix+3), e
      ld    (ix+0), h
      ld    (ix+1), l     
      ld    (ix+2), a
      
      ld    iy, tst_b
      
      ld    b, (iy+0)
      ld    c, (iy+1)
      ld    d, (iy+2)
      ld    e, (iy+3)
      ld    h, (iy+0)
      ld    l, (iy+1)
      ld    a, (iy+2)
      
      ret


test_02:
      ld    a, 0x02
      out   (0x01),a

      ld    a, 0x01
      ld    (tst_b), a
      
      ld    b, 0x02   
      ld    a, b
      ld    (tst_b), a
      ld    c, 0x03      
      ld    a, c
      ld    (tst_b), a
      
      ld    d, 0x04
      ld    a, d
      ld    (tst_b), a
      ld    e, 0x05
      ld    a, e
      ld    (tst_b), a
      
      ld    h, 0x04
      ld    (tst_b), a
      ld    a, h
      ld    l, 0x05
      ld    a, l
      ld    (tst_b), a
      
      ld    hl, tst_b
      ld    (hl), 0x06
      
      ret

test_03:
      ld    a, 0x03
      out   (0x01),a

      ld    bc, 0x0102
      ld    (tst_w), bc
      ld    de, 0x0304
      ld    (tst_w), de
      ld    hl, 0x0506
      ld    (tst_w), hl
      ld    ix, 0x0708
      ld    (tst_w), ix
      ld    iy, 0x090a
      ld    (tst_w), iy
      
      ret
      
      
test_04:
      ld    a, 0x04
      out   (0x01),a

      ld    bc, 0x0102
      ld    de, 0x0304
      ld    hl, 0x0506
      ld    a, 0x07
      
      ld    ix, tst_b
      ld    iy, tst_b
      
      ld    (ix + 0), a
      ld    (ix + 1), b
      ld    (ix + 2), c
      ld    (ix + 3), d
      ld    (ix + 0), e
      ld    (ix + 1), h
      ld    (ix + 2), l
      
      ld    iy, tst_b
      
      ld    (iy + 3), a
      ld    (iy + 0), b
      ld    (iy + 1), c
      ld    (iy + 2), d
      ld    (iy + 3), e
      ld    (iy + 0), h
      ld    (iy + 1), l
      
      ld    hl, tst_b
      ld    (hl), 0x01
      inc   hl
      ld    (hl), 0x02
      inc   hl
      ld    (hl), 0x03
      inc   hl
      ld    (hl), 0x04
      
      ld    a, (ix + 0)
      ld    b, (ix + 1)
      ld    c, (ix + 2)
      ld    d, (ix + 3)
      ld    e, (ix + 0)
      ld    h, (ix + 1)
      ld    l, (ix + 2)
      
      ld    a, (iy + 3)
      ld    b, (iy + 0)
      ld    c, (iy + 1)
      ld    d, (iy + 2)
      ld    e, (iy + 3)
      ld    h, (iy + 0)
      ld    l, (iy + 1)
      
      
      ld    (ix+1), 0x10
      ld    (iy+2), 0x11
      ld    (ix+3), 0x13
      
      ret

      
test_05:
      ld    a, 0x05
      out   (0x01),a
      
      ld    bc, tst_b
      ld    de, tst_b1
      
      ld    a, 0x20
      ld    (bc), a
      ld    a, 0x21
      ld    (de), a
      
      ld    a,(bc)
      ld    a,(de)
      
      ld    (tst_b), a
      ld    a, (tst_b)
      
      ld    a, i
      ld    i, a
      
      ld    a, r
      ld    r, a

      ret

test_06:
      ld    a, 0x06
      out   (0x01),a

      ld    bc, 0x0102
      ld    (tst_w), bc
      ld    bc, (tst_w)
      ld    de, 0x0304
      ld    (tst_w), de
      ld    de, (tst_w)
      ld    hl, 0x0506
      ld    (tst_w), hl
      ld    hl, (tst_w)
      
      di
      ld    (tst_w), sp
      call  m1
m1:   pop   hl
      ld    sp, 0
      ld    sp, hl 
      push  hl
      pop   ix
      ld    sp, ix
      push  hl
      pop   iy
      ld    sp, iy
      ld    sp, (tst_w)
      ei
            
      ld    ix, 0x0708
      ld    (tst_w), ix
      ld    ix, (tst_w)
      ld    iy, 0x090a
      ld    (tst_w), iy
      ld    iy, (tst_w)
      
      ld    hl, (tst_w)
      
      push  bc
      push  de
      push  hl
      push  af
      push  ix
      push  iy
      
      di
      nop
      ei
      
      pop   iy
      pop   ix
      pop   af
      pop   hl
      pop   de
      pop   bc
      
      ret

test_07:
      ld    a, 0x07
      out   (0x01),a

      ld    de, 0x0102
      ld    hl, 0x0304
      ex    de, hl
      
      ld    hl, 0x1020
      push  hl
      ld    hl, 0x3040
      push  hl
      
      pop   af
      ex    af, af'
      pop   af
      ex    af, af'
      
      ld    hl, 0x5060
      push  hl
      ld    hl, 0x0102
      ex    (sp), hl
      ld    (tst_w), hl
      ex    (sp), ix
      ld    (tst_w), ix
      ex    (sp), iy
      ld    (tst_w), iy      
      pop   hl
      
      ret

test_08:
      ld    a, 0x08
      out   (0x01),a

      // ldir
      ld    hl, buf_b
      ld    d,h
      ld    e,l
      inc   de
      ld    (hl), 0xaa
      ld    bc, 15
      ldir
      
      ld    (tst_w), hl
      ld    (tst_w), de
      ld    (tst_w), bc
      
      // lddr
      ld    hl, buf_e
      ld    d,h
      ld    e,l
      dec   de
      ld    bc, 15
      ld    (hl), 0x55
      lddr
      
      ld    (tst_w), hl
      ld    (tst_w), de
      ld    (tst_w), bc
      
      
      //ldi
      ld    hl, buf_b
      ld    de, buf_b + 1
      ld    bc, 15
      ld    (hl), 0x0f
      
      ldi
      ldi
      ldi
      ldi
      
      ld    (tst_w), hl
      ld    (tst_w), de
      ld    (tst_w), bc
      
      //ldd
      ld    hl, buf_e
      ld    de, buf_e - 1
      ld    bc, 0x0f
      ld    (hl), 0xf0
      
      ldd
      ldd
      ldd
      ldd
      
      ld    (tst_w), hl
      ld    (tst_w), de
      ld    (tst_w), bc
      
      // cpi
      ld    hl, buf_b
      ld    bc, 15
      ld    a, 0x0f
      
      cpi
      cpi
      cpi
      cpi
      push  af
      cpi
      push  af
      
      nop
      
      pop   af
      pop   af
      
      ld    (tst_w), bc
      ld    (tst_w), hl
      
      
      // cpd
      ld    hl, buf_e
      ld    bc, 15
      ld    a, 0xf0
      
      cpd
      cpd
      cpd
      cpd
      push  af
      cpd
      push  af
      
      nop
      
      pop   af
      pop   af
      
      ld    (tst_w), bc
      ld    (tst_w), hl
      
      // cpir
      ld    hl, buf_b
      ld    bc, 5
      ld    a, 0x0f
      
      cpir
      
      ld    (tst_w), bc
      ld    (tst_w), hl
      
      
      // cpir
      ld    hl, buf_e
      ld    bc, 5
      ld    a, 0xf0
      
      cpdr
      
      ld    (tst_w), bc
      ld    (tst_w), hl
      
      
      ret

test_09:
      ld    a, 0x09
      out   (0x01),a
      
      ld    ix, tst_b1
      ld    iy, tst_b1
      
      ld    (ix), 0x09
      ld    (iy), 0x0a
      
      
      // add
      ld    a, 0x07
      ld    bc, 0x0102
      ld    de, 0x0304
      ld    hl, 0x0506
      
      add   a, a
      add   a, b
      add   a, c
      add   a, d
      add   a, e
      add   a, h
      add   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      add   a, (hl)
      adc   a, (ix)
      adc   a, (iy+1)
      add   a, 0x0b
      ld    (tst_b), a

      
      //adc
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      adc   a, a
      adc   a, b
      adc   a, c
      adc   a, d
      adc   a, e
      adc   a, h
      adc   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      adc   a, (hl)
      adc   a, (ix)
      adc   a, (iy+1)
      adc   a, 0x0b
      ld    (tst_b), a
      
      
      //sub
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      sub   a, a
      sub   a, b
      sub   a, c
      sub   a, d
      sub   a, e
      sub   a, h
      sub   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      sub   a, (hl)
      sub   a, (ix)
      sub   a, (iy+1)
      sub   a, 0x0b
      ld    (tst_b), a
      
      
       //sbc
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      sbc   a, a
      sbc   a, b
      sbc   a, c
      sbc   a, d
      sbc   a, e
      sbc   a, h
      sbc   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      sbc   a, (hl)
      sbc   a, (ix)
      sbc   a, (iy+1)
      sbc   a, 0x0b
      ld    (tst_b), a
      
      
       //and
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      and   a, a
      and   a, b
      and   a, c
      and   a, d
      and   a, e
      and   a, h
      and   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      and   a, (hl)
      and   a, (ix)
      and   a, (iy+1)
      and   a, 0x0b
      ld    (tst_b), a
      
      
       //or
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      or    a, a
      or    a, b
      or    a, c
      or    a, d
      or    a, e
      or    a, h
      or    a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      or    a, (hl)
      or    a, (ix)
      or    a, (iy+1)
      or    a, 0x0b
      ld    (tst_b), a
      
      
      //xor
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      xor   a, a
      xor   a, b
      xor   a, c
      xor   a, d
      xor   a, e
      xor   a, h
      xor   a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      xor   a, (hl)
      xor   a, (ix)
      xor   a, (iy+1)
      xor   a, 0x0b
      ld    (tst_b), a
      
      
      //cp
      
      ld    a, 0x07
      ld    hl, 0x0506
      
      cp    a, a
      cp    a, b
      cp    a, c
      cp    a, d
      cp    a, e
      cp    a, h
      cp    a, l
      
      ld    hl, tst_b
      ld    (hl), 0x08
      cp    a, (hl)
      cp    a, (ix)
      cp    a, (iy+1)
      cp    a, 0x0b
      ld    (tst_b), a
      
      ld    ix, tst_b
      ld    iy, tst_b1
      
      ld    a, 0x01
      
      // inc
      inc   a
      ld    (ix), a
      ld    b, a
      
      inc   b
      ld    (ix), b
      ld    c, b
      
      inc   c
      ld    (ix), c
      ld    d, c
      
      inc   d
      ld    (ix), d
      ld    e, d
      
      inc   e
      ld    (ix), e
      ld    h, e
      
      inc   h
      ld    (ix), h
      ld    l, h
      
      inc   l
      ld    (ix), l
      
      inc   (ix)
      ld    a, (ix)
      ld    (iy),a
      inc   (iy)
      ld    hl, tst_b
      inc   (hl)

      
      // dec
      ld    a, 0xfe
      
      dec   a
      ld    (ix), a
      ld    b, a
      
      dec   b
      ld    (ix), b
      ld    c, b
      
      dec   c
      ld    (ix), c
      ld    d, c
      
      dec   d
      ld    (ix), d
      ld    e, d
      
      dec   e
      ld    (ix), e
      ld    h, e
      
      dec   h
      ld    (ix), h
      ld    l, h
      
      dec   l
      ld    (ix), l
      
      dec   (ix)
      ld    a, (ix)
      ld    (iy),a
      dec   (iy)
      ld    hl, tst_b
      dec   (hl)
      
      
      ret

test_10:
      ld    a, 10
      out   (0x01),a
      
      daa
      cpl
      neg
      ccf
      scf
      nop
      
      di
      im 0
      im 1
      im 2 
      im 0
      ei
      

      ret

test_11:
      ld    a, 11
      out   (0x01),a

      ret

test_12:
      ld    a, 12
      out   (0x01),a

      //hl
      ld    hl, 0      
      add   hl, sp
      ld    (tst_w), hl
      
      
      ld    hl, 0      
      ld    bc, 0x0101
      add   hl, bc
      ld    (tst_w), hl
      
      ld    hl, 0
      ld    de, 0x0202
      add   hl, de
      ld    (tst_w), hl
      
      ld    hl, 0
      ld    hl, 0x0303
      add   hl, hl
      ld    (tst_w), hl
      
      
      //ix
      ld    ix, 0      
      add   ix, sp
      ld    (tst_w), ix
      
      
      ld    ix, 0      
      ld    bc, 0x0101
      add   ix, bc
      ld    (tst_w), ix
      
      ld    ix, 0
      ld    de, 0x0202
      add   ix, de
      ld    (tst_w), ix
      
      ld    ix, 0
      ld    ix, 0x0303
      add   ix, ix
      ld    (tst_w), ix
      
      
      
      //iy
      ld    iy, 0      
      add   iy, sp
      ld    (tst_w), iy
      
      
      ld    iy, 0      
      ld    bc, 0x0101
      add   iy, bc
      ld    (tst_w), iy
      
      ld    iy, 0
      ld    de, 0x0202
      add   iy, de
      ld    (tst_w), iy
      
      ld    iy, 0
      ld    iy, 0x0303
      add   iy, iy
      ld    (tst_w), iy
      
      ld    hl, 0x0102
      ld    de, 0x0304
      ld    bc, 0x0506
      ld    ix, 0x0708
      ld    iy, 0x090a
      
      inc   hl
      ld    (tst_w), hl
      
      inc   ix
      ld    (tst_w), ix
      
      inc   iy
      ld    (tst_w), iy
      
      inc   de
      ld    (tst_w), de
      
      inc   bc
      ld    (tst_w), bc
      
      dec   hl
      ld    (tst_w), hl
      
      dec   ix
      ld    (tst_w), ix
      
      dec   iy
      ld    (tst_w), iy
      
      dec   de
      ld    (tst_w), de
      
      dec   bc
      ld    (tst_w), bc
      
      ret

test_13:
      ld    a, 13
      out   (0x01),a

      ld    a, 0xAA
      rlca
      rla
      rrca
      rra
      
      push  af
      push  hl
      
      pop   hl
      pop   af
      
      ld    hl, tst_w
      ld    (hl), 0x08
      push  hl
      pop   ix
      ld    (ix+1), 0x09
      push  hl
      pop   iy
      ld    (iy+2), 0x0a
      
      ld    bc, 0x0102
      ld    de, 0x0304
      ld    hl, 0x0506
      ld    a, 0x07
      
      //rlc
      ld    hl, 0x0506
      rlc   b
      rlc   c
      rlc   d
      rlc   e
      rlc   h
      rlc   l
      rlc   a
      ld    hl, tst_w
      rlc   (hl)
      rlc   (ix+1)
      rlc   (ix+2)
      
      //rrc
      ld    hl, 0x0506
      rrc   b
      rrc   c
      rrc   d
      rrc   e
      rrc   h
      rrc   l
      rrc   a
      ld    hl, tst_w
      rrc   (hl)
      rrc   (ix+1)
      rrc   (ix+2)
      
      //rl
      ld    hl, 0x0506
      rl    b
      rl    c
      rl    d
      rl    e
      rl    h
      rl    l
      rl    a
      ld    hl, tst_w
      rl    (hl)
      rl    (ix+1)
      rl    (ix+2)
      
      
      //rr
      ld    hl, 0x0506
      rr    b
      rr    c
      rr    d
      rr    e
      rr    h
      rr    l
      rr    a
      ld    hl, tst_w
      rr    (hl)
      rr    (ix+1)
      rr    (ix+2)
      
      
      //sla
      ld    hl, 0x0506
      sla   b
      sla   c
      sla   d
      sla   e
      sla   h
      sla   l
      sla   a
      ld    hl, tst_w
      sla   (hl)
      sla   (ix+1)
      sla   (ix+2)
      
      //sra
      ld    hl, 0x0506
      sra   b
      sra   c
      sra   d
      sra   e
      sra   h
      sra   l
      sra   a
      ld    hl, tst_w
      sra   (hl)
      sra   (ix+1)
      sra   (ix+2)
      
      //sll
      ld    hl, 0x0506
      sll   b
      sll   c
      sll   d
      sll   e
      sll   h
      sll   l
      sll   a
      ld    hl, tst_w
      sll   (hl)
      sll   (ix+1)
      sll   (ix+2)
      
      //srl
      ld    hl, 0x0506
      srl   b
      srl   c
      srl   d
      srl   e
      srl   h
      srl   l
      srl   a
      ld    hl, tst_w
      srl   (hl)
      srl   (ix+1)
      srl   (ix+2)
      
      rld
      rrd
      
      
      ret
      
test_14:
      ld    a, 14
      out   (0x01),a

      
      ld    hl, tst_w
      ld    (hl), 0x08
      push  hl
      pop   ix
      ld    (ix+1), 0x09
      push  hl
      pop   iy
      ld    (iy+2), 0x0a
      
      ld    bc, 0x0102
      ld    de, 0x0304
      ld    hl, 0x0506
      ld    a, 0x07
      
      //=0=
      
      //bit
      ld    hl, 0x0506
      bit   0, b
      bit   0, c
      bit   0, d
      bit   0, e
      bit   0, h
      bit   0, l
      bit   0, a
      ld    hl, tst_w
      bit   0, (hl)
      bit   0, (ix+1)
      bit   0, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   0, b
      set   0, c
      set   0, d
      set   0, e
      set   0, h
      set   0, l
      set   0, a
      ld    hl, tst_w
      set   0, (hl)
      set   0, (ix+1)
      set   0, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   0, b
      res   0, c
      res   0, d
      res   0, e
      res   0, h
      res   0, l
      res   0, a
      ld    hl, tst_w
      res   0, (hl)
      res   0, (ix+1)
      res   0, (iy+2)
      
      //=1=
      
      //bit
      ld    hl, 0x0506
      bit   1, b
      bit   1, c
      bit   1, d
      bit   1, e
      bit   1, h
      bit   1, l
      bit   1, a
      ld    hl, tst_w
      bit   1, (hl)
      bit   1, (ix+1)
      bit   1, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   1, b
      set   1, c
      set   1, d
      set   1, e
      set   1, h
      set   1, l
      set   1, a
      ld    hl, tst_w
      set   1, (hl)
      set   1, (ix+1)
      set   1, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   1, b
      res   1, c
      res   1, d
      res   1, e
      res   1, h
      res   1, l
      res   1, a
      ld    hl, tst_w
      res   1, (hl)
      res   1, (ix+1)
      res   1, (iy+2)
      
      //=2=
      
      //bit
      ld    hl, 0x0506
      bit   2, b
      bit   2, c
      bit   2, d
      bit   2, e
      bit   2, h
      bit   2, l
      bit   2, a
      ld    hl, tst_w
      bit   2, (hl)
      bit   2, (ix+1)
      bit   2, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   2, b
      set   2, c
      set   2, d
      set   2, e
      set   2, h
      set   2, l
      set   2, a
      ld    hl, tst_w
      set   2, (hl)
      set   2, (ix+1)
      set   2, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   2, b
      res   2, c
      res   2, d
      res   2, e
      res   2, h
      res   2, l
      res   2, a
      ld    hl, tst_w
      res   2, (hl)
      res   2, (ix+1)
      res   2, (iy+2)
      
      //=3=
      
      //bit
      ld    hl, 0x0506
      bit   3, b
      bit   3, c
      bit   3, d
      bit   3, e
      bit   3, h
      bit   3, l
      bit   3, a
      ld    hl, tst_w
      bit   3, (hl)
      bit   3, (ix+1)
      bit   3, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   3, b
      set   3, c
      set   3, d
      set   3, e
      set   3, h
      set   3, l
      set   3, a
      ld    hl, tst_w
      set   3, (hl)
      set   3, (ix+1)
      set   3, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   3, b
      res   3, c
      res   3, d
      res   3, e
      res   3, h
      res   3, l
      res   3, a
      ld    hl, tst_w
      res   3, (hl)
      res   3, (ix+1)
      res   3, (iy+2)
      
      //=4=
      
      //bit
      ld    hl, 0x0506
      bit   4, b
      bit   4, c
      bit   4, d
      bit   4, e
      bit   4, h
      bit   4, l
      bit   4, a
      ld    hl, tst_w
      bit   4, (hl)
      bit   4, (ix+1)
      bit   4, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   4, b
      set   4, c
      set   4, d
      set   4, e
      set   4, h
      set   4, l
      set   4, a
      ld    hl, tst_w
      set   4, (hl)
      set   4, (ix+1)
      set   4, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   4, b
      res   4, c
      res   4, d
      res   4, e
      res   4, h
      res   4, l
      res   4, a
      ld    hl, tst_w
      res   4, (hl)
      res   4, (ix+1)
      res   4, (iy+2)
      
      //=5=
      
      //bit
      ld    hl, 0x0506
      bit   5, b
      bit   5, c
      bit   5, d
      bit   5, e
      bit   5, h
      bit   5, l
      bit   5, a
      ld    hl, tst_w
      bit   5, (hl)
      bit   5, (ix+1)
      bit   5, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   5, b
      set   5, c
      set   5, d
      set   5, e
      set   5, h
      set   5, l
      set   5, a
      ld    hl, tst_w
      set   5, (hl)
      set   5, (ix+1)
      set   5, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   5, b
      res   5, c
      res   5, d
      res   5, e
      res   5, h
      res   5, l
      res   5, a
      ld    hl, tst_w
      res   5, (hl)
      res   5, (ix+1)
      res   5, (iy+2)
      
      
      //=6=
            
      //bit
      ld    hl, 0x0506
      bit   6, b
      bit   6, c
      bit   6, d
      bit   6, e
      bit   6, h
      bit   6, l
      bit   6, a
      ld    hl, tst_w
      bit   6, (hl)
      bit   6, (ix+1)
      bit   6, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   6, b
      set   6, c
      set   6, d
      set   6, e
      set   6, h
      set   6, l
      set   6, a
      ld    hl, tst_w
      set   6, (hl)
      set   6, (ix+1)
      set   6, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   6, b
      res   6, c
      res   6, d
      res   6, e
      res   6, h
      res   6, l
      res   6, a
      ld    hl, tst_w
      res   6, (hl)
      res   6, (ix+1)
      res   6, (iy+2)
      
      //=7=
      
      //bit
      ld    hl, 0x0506
      bit   7, b
      bit   7, c
      bit   7, d
      bit   7, e
      bit   7, h
      bit   7, l
      bit   7, a
      ld    hl, tst_w
      bit   7, (hl)
      bit   7, (ix+1)
      bit   7, (iy+2)
      
      //set
      ld    hl, 0x0506
      set   7, b
      set   7, c
      set   7, d
      set   7, e
      set   7, h
      set   7, l
      set   7, a
      ld    hl, tst_w
      set   7, (hl)
      set   7, (ix+1)
      set   7, (iy+2)
      
      //res
      ld    hl, 0x0506
      res   7, b
      res   7, c
      res   7, d
      res   7, e
      res   7, h
      res   7, l
      res   7, a
      ld    hl, tst_w
      res   7, (hl)
      res   7, (ix+1)
      res   7, (iy+2)
      
      ret
      
      

test_15:
      ld    a, 15
      out   (0x01),a
      
      jp    m2
      nop
m2:   jr    m3
      nop
   

f_res equ   0x0000
f_c   equ   0x0001
f_n   equ   0x0002
f_pv  equ   0x0004
f_h   equ   0x0010
f_z   equ   0x0040
f_s   equ   0x0080


m3:   di

      // jp cc
      ld    hl, f_res
      push  hl
      pop   af
      jp    z, hlt
      jp    nz, m4
      halt
m4:   jp    c, hlt
      jp    nc, m5
      halt
m5:   jp    pe, hlt
      jp    po, m6
      halt
m6:   jp    m, hlt
      jp    p, m7
      halt
      
m7:   ld    hl, f_c
      push  hl
      pop   af
      jp    nc, hlt
      jp    c, m8
      halt
      
m8:   ld    hl, f_z
      push  hl
      pop   af
      jp    nz, hlt
      jp    z, m9
      halt  
      
m9:   ld    hl, f_pv
      push  hl
      pop   af
      jp    po, hlt
      jp    pe, m10
      halt      
      
m10:  ld    hl, f_s
      push  hl
      pop   af
      jp    p, hlt
      jp    m, m11
      halt      
          
      
      // jr
m11:  ld    hl, f_res
      push  hl
      pop   af
      jr    c, h1
      jr    nc, m12
h1:   halt   
      
m12:  jr    z, h1
      jr    nz, m13
      halt 
      
m13:  ld    hl, f_z
      push  hl
      pop   af
      jr    nz, h1
      jr    z, m14
      halt      
      
m14:  ld    hl, f_c
      push  hl
      pop   af
      jr    nc, h1
      jr    c, m15
      halt            

m15:  ld    hl, m16
      jp    (hl)

m16:  ld    ix, m17
      jp    (ix)

m17:  ld    iy, m18
      jp    (iy)
      
m18:  ld    hl, tst_b
      ld    bc, 0x0500    
m18a: ld    (hl), b
      djnz  m18a
      
      ei

      ret

      
      
test_16:
      di

      ld    a, 16
      out   (0x01),a
      
           
      
      ld    hl, f_res
      push  hl
      
      // call cc
      
      pop   af
      call  c, hlt
      call  nc, m19
      halt
      
m19:  pop   de
      call  z, hlt
      call  nz, m20
      halt
      
m20:  pop   de
      call  pe, hlt
      call  po, m21
      halt
      
m21:  pop   de
      call  m, hlt
      call  p, m22
      halt
      
m22:  pop   de
      ld    hl, f_c
      push  hl
      pop   af
      call  nc, hlt
      call  c, m23
      halt
      
m23:  pop   de
      ld    hl, f_z
      push  hl
      pop   af
      call  nz, hlt
      call  z, m24
      halt

m24:  pop   de
      ld    hl, f_pv
      push  hl
      pop   af
      call  po, hlt
      call  pe, m25
      halt
      
m25:  pop   de
      ld    hl, f_s
      push  hl
      pop   af
      call  p, hlt
      call  m, m26
      halt
      
      // ret cc
m26:  pop   de
      ld    bc, hlt


      ld    hl, f_res
      push  hl
      pop   af
      push  bc
      ret   c
      pop   bc
      ld    hl, m27
      push  hl
      ret   nc
      halt
      
m27:  push  bc
      ret   z
      pop   bc
      ld    hl, m28
      push  hl
      ret   nz
      halt      
      
m28:  push  bc
      ret   pe
      pop   bc
      ld    hl, m29
      push  hl
      ret   po
      halt            
      
m29:  push  bc
      ret   m
      pop   bc
      ld    hl, m30
      push  hl
      ret   p
      halt            
      
m30:  ld    hl, f_c
      push  hl
      pop   af
      push  bc
      ret   nc
      pop   bc
      ld    hl, m31
      push  hl
      ret   c
      halt
      
m31:  ld    hl, f_z
      push  hl
      pop   af
      push  bc
      ret   nz
      pop   bc
      ld    hl, m32
      push  hl
      ret   z
      halt   

m32:  ld    hl, f_pv
      push  hl
      pop   af
      push  bc
      ret   po
      pop   bc
      ld    hl, m33
      push  hl
      ret   pe
      halt      
      
m33:  ld    hl, f_s
      push  hl
      pop   af
      push  bc
      ret   p
      pop   bc
      ld    hl, m34
      push  hl
      ret   m
      halt      
    
      // call ret
    
m34:  call   m35
      halt
m35:  pop   de
      ld    hl, m36
      push  hl
      ret
      halt
      
      rst 0x18 // rst
      rst 0x20 // reti
      rst 0x28 // retn      
      
m36:  ei

      ret
      
hlt:  halt      

test_17:
      ld    a, 17
      out   (0x01),a
      
      // in
      ld    a, 0
      in    a, (0x02)
      ld    (tst_b), a
      
      ld    bc, 0x0003
      
      in    a, (c)
      in    d, (c)
      in    e, (c)
      in    h, (c)
      in    l, (c)
      in    b, (c)
      ld    b, 0x00
      in    c, (c)
      
      //out
      ld    a, 0x55
      out   (0x02), a
      
      ld    bc, 0x0003
      ld    de, 0x0405
      ld    hl, 0x0607
      
      out   (c), b
      out   (c), c
      out   (c), d
      out   (c), e
      out   (c), h
      out   (c), l
      
      
      // ini
      ld    hl, buf_b
      ld    bc, 0x01FF
      ini
      ini
      ini
      ini
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      // ind
      ld    hl, buf_e
      ld    bc, 0x01FF
      ind
      ind
      ind
      ind
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      //outi
      ld    hl, buf_b
      ld    bc, 0x01FF
      outi
      outi
      outi
      outi
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      //outd
      ld    hl, buf_e
      ld    bc, 0x01FF
      outd
      outd
      outd
      outd
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      
      //inir
      ld    hl, buf_b
      ld    bc, 0x05FF
      inir
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      //indr
      ld    hl, buf_e
      ld    bc, 0x05FF
      inir
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      //inir
      ld    hl, buf_b
      ld    bc, 0x05FF
      otir
      ld    (tst_w), hl
      ld    (tst_w), bc
      
      //indr
      ld    hl, buf_e
      ld    bc, 0x05FF
      otdr
      ld    (tst_w), hl
      ld    (tst_w), bc
      

      ret      
      

bdos:
      push	af
      push	bc
      push	de
      push	hl
      ; Accept call 2 (print char) and call 9 (print string)
      ; Ignore all others
      ld	b,a		; save char (destroys B)
      ld	a,c
      cp	2
      jr	z,prchar
      cp	9
      jr	z,prstring
bdosdone: 
      pop	hl
      pop	de
      pop	bc
      pop	af
      ret

      ; Pass bdos calls to Spectrum system
prchar: 
      ld	a,b		; get char back
      cp	10	; ignore LF as CR auto-LFs
      jr	z,bdosdone
      rst	0x10
      jr	bdosdone

prstring: 
      ld	a,(de)
      cp	0
      jr	z,bdosdone
      cp	10
      call    nz,0x10
      inc	de
      jr	prstring 


      ds      32
STACK:


END:

      savebin "rom.bin", 0x0000, END-BEGIN
